// cs lights and shadows
//
// Generated by Microsoft (R) D3D Shader Disassembler
//
//   using 3Dmigoto v0.6.164 on Sun Nov  8 11:19:55 2026
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_0
dcl_globalFlags refactoringAllowed
dcl_immediateConstantBuffer { { 1.000000, 0, 0, 0},
                              { 0, 1.000000, 0, 0},
                              { 0, 0, 1.000000, 0},
                              { 0, 0, 0, 1.000000} }
dcl_constantbuffer CB0[36], dynamicIndexed
dcl_resource_texture2darray (float,float,float,float) t0
dcl_resource_structured t1, 16
dcl_resource_structured t2, 96
dcl_resource_structured t3, 56
dcl_resource_structured t4, 4
dcl_resource_texture2d (float,float,float,float) t125
dcl_uav_structured u0, 4
dcl_uav_structured u1, 4
dcl_input vThreadIDInGroupFlattened
dcl_input vThreadGroupID.xy
dcl_input vThreadID.z
dcl_temps 16
dcl_indexableTemp x0[2], 4
dcl_indexableTemp x1[5], 4
dcl_tgsm_structured g0, 4, 64
dcl_tgsm_structured g1, 4, 64
dcl_tgsm_raw g2, 4
dcl_tgsm_raw g3, 4
dcl_tgsm_raw g4, 4
dcl_tgsm_structured g5, 4, 2
dcl_tgsm_raw g6, 4
dcl_tgsm_structured g7, 4, 5
dcl_tgsm_raw g8, 4
dcl_tgsm_raw g9, 4
dcl_thread_group 64, 1, 1
store_structured g1.x, vThreadIDInGroupFlattened.x, l(0), l(0)
iadd r0.xyzw, cb0[33].xyxy, l(15, 15, -1, -1)
ushr r0.xy, r0.xyxx, l(4, 4, 0, 0)
if_z vThreadIDInGroupFlattened.x
  store_raw g2.x, l(0), l(340282346638528859811704183484516925440.000000)
  store_raw g3.x, l(0), l(0)
  store_raw g4.x, l(0), l(0)
endif
sync_g_t
ishl r1.xy, vThreadGroupID.xyxx, l(4, 4, 0, 0)
bfi r2.x, l(28), l(4), vThreadGroupID.x, vThreadIDInGroupFlattened.x
ishr r1.z, vThreadIDInGroupFlattened.x, l(4)
imad r2.y, vThreadGroupID.y, l(16), r1.z
umin r2.xy, r0.zwzz, r2.xyxx
mov r2.z, vThreadID.z
mov r2.w, l(0)
ld_indexable(texture2darray)(float,float,float,float) r1.z, r2.xyzw, t0.yzxw
add r1.z, -r1.z, l(1.000000)
ishl r3.xy, vThreadID.zzzz, l(2, 1, 0, 0)
mad r3.zw, cb0[r3.x + 2].zzzw, r1.zzzz, cb0[r3.x + 3].zzzw
div r4.x, r3.z, r3.w
lt r1.w, r1.z, l(1.000000)
min r5.x, r1.z, l(340282346638528859811704183484516925440.000000)
max r5.y, r1.z, l(0.000000)
movc r1.zw, r1.wwww, r5.xxxy, l(0,0,340282346638528859811704183484516925440.000000,0)
iadd r5.xyz, vThreadIDInGroupFlattened.xxxx, l(64, 128, 192, 0)
bfi r6.xyz, l(28, 28, 28, 0), l(4, 4, 4, 0), vThreadGroupID.xxxx, r5.xyzx
ishr r5.xyz, r5.xyzx, l(4, 4, 4, 0)
imad r5.xyz, vThreadGroupID.yyyy, l(16, 16, 16, 0), r5.xzyx
mov r6.w, r5.x
umin r2.xy, r0.zwzz, r6.xwxx
ld_indexable(texture2darray)(float,float,float,float) r3.z, r2.xyzw, t0.yzxw
add r3.z, -r3.z, l(1.000000)
mad r6.xw, cb0[r3.x + 2].zzzw, r3.zzzz, cb0[r3.x + 3].zzzw
div r4.y, r6.x, r6.w
lt r3.w, r3.z, l(1.000000)
min r7.x, r1.z, r3.z
max r7.y, r1.w, r3.z
movc r1.zw, r3.wwww, r7.xxxy, r1.zzzw
mov r5.xw, r6.zzzy
umin r2.xy, r0.zwzz, r5.wzww
ld_indexable(texture2darray)(float,float,float,float) r3.z, r2.xyzw, t0.yzxw
add r3.z, -r3.z, l(1.000000)
mad r5.zw, cb0[r3.x + 2].zzzw, r3.zzzz, cb0[r3.x + 3].zzzw
div r4.z, r5.z, r5.w
lt r3.w, r3.z, l(1.000000)
min r6.x, r1.z, r3.z
max r6.y, r1.w, r3.z
movc r1.zw, r3.wwww, r6.xxxy, r1.zzzw
umin r2.xy, r0.zwzz, r5.xyxx
ld_indexable(texture2darray)(float,float,float,float) r2.x, r2.xyzw, t0.xyzw
add r2.x, -r2.x, l(1.000000)
mad r2.yz, cb0[r3.x + 2].zzwz, r2.xxxx, cb0[r3.x + 3].zzwz
div r4.w, r2.y, r2.z
lt r2.y, r2.x, l(1.000000)
min r5.x, r1.z, r2.x
max r5.y, r1.w, r2.x
movc r1.zw, r2.yyyy, r5.xxxy, r1.zzzw
atomic_umax g3, l(0), r1.w
atomic_umin g2, l(0), r1.z
sync_g_t
utof r1.zw, r1.xxxy
utof r2.xy, cb0[33].xyxx
div r5.xy, r1.zwzz, r2.xyxx
ld_raw r5.z, l(0), g2.xxxx
iadd r1.xz, r1.xxyx, l(16, 0, 16, 0)
utof r1.xz, r1.xxzx
div r1.xz, r1.xxzx, r2.xxyx
ld_raw r2.z, l(0), g3.xxxx
min r2.xy, r1.xzxx, l(1.000000, 1.000000, 0.000000, 0.000000)
iadd r1.xz, r0.xxyx, l(3, 0, 3, 0)
ushr r1.xz, r1.xxzx, l(2, 0, 2, 0)
imul null, r1.w, r1.x, vThreadID.z
ushr r3.zw, vThreadGroupID.yyyx, l(0, 0, 2, 2)
imul null, r1.x, r1.x, r3.z
imad r1.x, r1.w, r1.z, r1.x
iadd r1.x, r3.w, r1.x
ishl r1.x, r1.x, l(9)
ld_structured_indexable(structured_buffer, stride=4)(mixed,mixed,mixed,mixed) r1.z, r1.x, l(0), t4.xxxx
// ---- STEREO FIX: widen tile UV rect (x) by max disparity over tile depth range ----
ld_indexable(texture2d)(float,float,float,float) r6.xyzw, l(0, 0, 0, 0), t125.xyzw
min r7.x, r5.z, l(1.000000)
max r7.y, r2.z, l(0.000000)
mad r8.xy, cb0[r3.x + 2].zwzz, r7.xxxx, cb0[r3.x + 3].zwzz
div r8.x, r8.x, r8.y
mad r8.yz, cb0[r3.x + 2].xzwx, r7.yyyy, cb0[r3.x + 3].xzwx
div r8.y, r8.y, r8.z
div r8.xy, r6.yyyy, r8.xyxx
add r8.xy, -r8.xyxx, l(1.000000, 1.000000, 0, 0)
mul r8.xy, r8.xyxx, r6.xxxx
max r8.z, |r8.x|, |r8.y|
mul r8.z, r8.z, l(0.500000)
min r8.z, r8.z, l(0.500000)
add r5.x, r5.x, -r8.z
add r2.x, r2.x, r8.z
// ---- /STEREO FIX ----
mov r1.w, vThreadIDInGroupFlattened.x
loop
  ige r2.w, r1.w, r1.z
  breakc_nz r2.w
  iadd r2.w, r1.w, r1.x
  iadd r2.w, r2.w, l(1)
  ld_structured_indexable(structured_buffer, stride=4)(mixed,mixed,mixed,mixed) r2.w, r2.w, l(0), t4.xxxx
  ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r3.z, r2.w, l(28), t2.xxxx
  ieq r3.z, r3.z, l(5)
  if_nz r3.z
    break
  endif
  imad r3.z, r3.y, cb0[33].z, r2.w
  iadd r3.w, r3.z, cb0[33].z
  ld_structured_indexable(structured_buffer, stride=16)(mixed,mixed,mixed,mixed) r6.xyz, r3.z, l(0), t1.xyzx
  ld_structured_indexable(structured_buffer, stride=16)(mixed,mixed,mixed,mixed) r7.xyz, r3.w, l(0), t1.xyzx
  lt r7.xyz, r5.xyzx, r7.xyzx
  and r3.z, r7.y, r7.x
  and r3.z, r7.z, r3.z
  lt r6.xyz, r6.xyzx, r2.xyzx
  and r3.w, r6.y, r6.x
  and r3.w, r6.z, r3.w
  and r3.z, r3.w, r3.z
  if_nz r3.z
    imm_atomic_iadd r6.x, g4, l(0), l(1)
    ult r3.z, r6.x, l(64)
    if_nz r3.z
      store_structured g0.x, r6.x, l(0), r2.w
    endif
  endif
  iadd r1.w, r1.w, l(64)
endloop
ult r1.xzw, vThreadIDInGroupFlattened.xxxx, l(2, 0, 32, 5)
if_nz r1.x
  store_structured g5.x, vThreadIDInGroupFlattened.x, l(0), l(0)
endif
sync_g_t
ld_raw r1.x, l(0), g4.xxxx
umin r1.x, r1.x, l(64)
imad r2.xy, vThreadGroupID.xyxx, l(16, 16, 0, 0), l(8, 8, 0, 0)
umin r2.xy, r0.zwzz, r2.xyxx
utof r2.xy, r2.xyxx
if_z vThreadIDInGroupFlattened.x
  store_raw g8.x, l(0), l(0)
endif
mov r2.z, vThreadIDInGroupFlattened.x
loop
  ige r2.w, r2.z, r1.x
  breakc_nz r2.w
  ld_structured r2.w, r2.z, l(0), g0.xxxx
  store_structured g1.x, r2.z, l(0), r2.w
  iadd r2.z, r2.z, l(64)
endloop
sync_g_t
movc r2.zw, cb0[33].wwww, cb0[r3.x + 11].xxxy, cb0[r3.x + 10].xxxy
add r2.xy, -r2.zwzz, r2.xyxx
div r2.x, r2.x, cb0[r3.x + 8].x
div r2.y, r2.y, cb0[r3.x + 9].y
div r5.x, l(1.000000, 1.000000, 1.000000, 1.000000), cb0[r3.x + 8].x
div r5.y, l(1.000000, 1.000000, 1.000000, 1.000000), cb0[r3.x + 9].y
dp2 r3.y, r5.xyxx, r5.xyxx
sqrt r3.y, r3.y
mul r3.y, r3.y, l(8.000000)
iadd r3.z, cb0[33].z, l(-1)
movc r5.xy, cb0[33].wwww, l(0,0,0,0), r2.xyxx
movc r2.xy, cb0[33].wwww, -r2.xyxx, l(-0.000000,-0.000000,0,0)
mov r5.z, l(1.000000)
dp3 r3.w, r5.xyzx, r5.xyzx
mov r5.w, vThreadIDInGroupFlattened.x
loop
  ige r6.x, r5.w, r1.x
  breakc_nz r6.x
  ld_structured r6.x, r5.w, l(0), g1.xxxx
  umin r6.y, r3.z, r6.x
  imad r6.y, vThreadID.z, cb0[33].z, r6.y
  ld_structured_indexable(structured_buffer, stride=56)(mixed,mixed,mixed,mixed) r7.xyz, r6.y, l(36), t3.xyzx
  ld_structured_indexable(structured_buffer, stride=56)(mixed,mixed,mixed,mixed) r6.y, r6.y, l(52), t3.xxxx
  add r7.xy, r2.xyxx, r7.xyxx
  mul r8.xy, r7.xyxx, -r7.zzzz
  dp2 r8.z, r7.xyxx, r7.xyxx
  dp3 r6.z, r8.xyzx, r8.xyzx
  sqrt r6.z, r6.z
  lt r6.w, l(0.000100), r6.z
  div r7.w, r8.z, r6.z
  movc r6.z, r6.w, r7.w, r6.z
  mad r6.z, r6.z, r6.y, r7.z
  movc r6.z, cb0[33].w, l(1.000000), r6.z
  mad r6.y, r6.z, r3.y, r6.y
  dp3 r6.z, r7.xyzx, r5.xyzx
  dp3 r6.w, r7.xyzx, r7.xyzx
  mad r6.y, -r6.y, r6.y, r6.w
  mul r6.w, r3.w, r6.y
  mad r6.w, r6.z, r6.z, -r6.w
  lt r6.y, r6.y, l(0.000000)
  lt r6.zw, l(0.000000, 0.000000, 0.000000, 0.000000), r6.zzzw
  and r6.z, r6.z, r6.w
  or r6.y, r6.z, r6.y
  mov r6.y, l(-1)
  if_nz r6.y
    imm_atomic_iadd r7.x, g8, l(0), l(1)
    store_structured g0.x, r7.x, l(0), r6.x
  endif
  iadd r5.w, r5.w, l(64)
endloop
sync_g_t
ld_raw r1.x, l(0), g8.xxxx
mov x0[0].x, l(0)
mov x0[1].x, l(0)
mov r2.x, l(0)
loop
  ige r2.y, r2.x, r1.x
  breakc_nz r2.y
  ilt r2.y, r2.x, r1.x
  ld_structured r3.y, r2.x, l(0), g0.xxxx
  umin r3.y, r3.z, r3.y
  imad r3.y, vThreadID.z, cb0[33].z, r3.y
  and r3.y, r2.y, r3.y
  ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r3.w, r3.y, l(12), t2.xxxx
  and r2.y, r2.y, r3.w
  mov r3.w, r2.x
  mov r5.x, r3.y
  mov r5.y, r2.y
  loop
    ilt r5.z, r3.w, r1.x
    ieq r5.w, r5.y, l(0)
    and r5.z, r5.w, r5.z
    breakc_z r5.z
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r6.xyz, r5.x, l(0), t2.xyzx
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r7.xyz, r5.x, l(16), t2.xyzx
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r8.xyzw, r5.x, l(32), t2.xyzw
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r9.xyzw, r5.x, l(48), t2.xyzw
    mov r10.x, r8.w
    mov r5.zw, l(0,0,0,0)
    loop
      ige r6.w, r5.w, l(4)
      breakc_nz r6.w
      imad r6.w, r5.w, l(64), vThreadIDInGroupFlattened.x
      bfi r11.x, l(28), l(4), vThreadGroupID.x, r6.w
      ishr r6.w, r6.w, l(4)
      iadd r11.y, r1.y, r6.w
      umin r10.zw, r0.zzzw, r11.xxxy
      utof r10.zw, r10.zzzw
      add r10.zw, -r2.zzzw, r10.zzzw
      dp4 r11.z, r4.xyzw, icb[r5.w + 0].xyzw
      add r10.zw, r10.zzzw, l(0.000000, 0.000000, 0.500000, 0.500000)
      div r12.x, r10.z, cb0[r3.x + 8].x
      div r12.y, r10.w, cb0[r3.x + 9].y
      mul r10.zw, r11.zzzz, r12.xxxy
      movc r11.xy, cb0[33].wwww, r12.xyxx, r10.zwzz
      add r11.xyz, -r6.xyzx, r11.xyzx
      dp3 r12.x, r11.xyzx, r11.xyzx
      dp3 r10.y, r11.xyzx, r9.xyzx
      dp3 r13.x, r11.xyzx, r7.xyzx
      dp3 r13.y, r11.xyzx, r8.xyzx
      dp2 r6.w, |r13.xyxx|, |r13.xyxx|
      sqrt r6.w, r6.w
      mul r12.y, r9.w, r6.w
      lt r10.yz, r12.xxyx, r10.xxyx
      and r6.w, r10.z, r10.y
      mov r6.w, l(-1)
      movc r5.z, r6.w, l(1), r5.z
      iadd r5.w, r5.w, l(1)
    endloop
    ilt r5.w, r3.w, l(32)
    movc r5.w, r5.w, l(0), l(1)
    ishl r6.x, r5.z, r3.w
    mov r6.y, x0[r5.w + 0].x
    or r6.x, r6.x, r6.y
    mov x0[r5.w + 0].x, r6.x
    iadd r3.w, r3.w, l(1)
    ilt r5.w, r3.w, r1.x
    ld_structured r6.x, r3.w, l(0), g0.xxxx
    umin r6.x, r3.z, r6.x
    imad r6.x, vThreadID.z, cb0[33].z, r6.x
    and r5.x, r5.w, r6.x
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r6.x, r5.x, l(12), t2.xxxx
    and r5.y, r5.w, r6.x
  endloop
  mov r2.y, r3.w
  mov r3.y, r5.x
  mov r5.w, r5.y
  loop
    ilt r6.x, r2.y, r1.x
    ieq r6.y, r5.w, l(1)
    and r6.x, r6.y, r6.x
    breakc_z r6.x
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r6.xyz, r3.y, l(0), t2.xyzx
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r6.w, r3.y, l(44), t2.xxxx
    mov r7.xy, l(0,0,0,0)
    loop
      ige r7.z, r7.y, l(4)
      breakc_nz r7.z
      imad r7.z, r7.y, l(64), vThreadIDInGroupFlattened.x
      bfi r8.x, l(28), l(4), vThreadGroupID.x, r7.z
      ishr r7.z, r7.z, l(4)
      iadd r8.y, r1.y, r7.z
      umin r7.zw, r0.zzzw, r8.xxxy
      utof r7.zw, r7.zzzw
      add r7.zw, -r2.zzzw, r7.zzzw
      dp4 r8.z, r4.xyzw, icb[r7.y + 0].xyzw
      add r7.zw, r7.zzzw, l(0.000000, 0.000000, 0.500000, 0.500000)
      div r9.x, r7.z, cb0[r3.x + 8].x
      div r9.y, r7.w, cb0[r3.x + 9].y
      mul r7.zw, r8.zzzz, r9.xxxy
      movc r8.xy, cb0[33].wwww, r9.xyxx, r7.zwzz
      add r8.xyz, r6.xyzx, -r8.xyzx
      dp3 r7.z, r8.xyzx, r8.xyzx
      lt r7.z, r7.z, r6.w
      mov r7.z, l(-1)
      movc r7.x, r7.z, l(1), r7.x
      iadd r7.y, r7.y, l(1)
    endloop
    ilt r6.x, r2.y, l(32)
    movc r6.x, r6.x, l(0), l(1)
    ishl r6.y, r7.x, r2.y
    mov r6.z, x0[r6.x + 0].x
    or r6.y, r6.y, r6.z
    mov x0[r6.x + 0].x, r6.y
    iadd r2.y, r2.y, l(1)
    ilt r6.x, r2.y, r1.x
    ld_structured r6.y, r2.y, l(0), g0.xxxx
    umin r6.y, r3.z, r6.y
    imad r6.y, vThreadID.z, cb0[33].z, r6.y
    and r3.y, r6.y, r6.x
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r6.y, r3.y, l(12), t2.xxxx
    and r5.w, r6.y, r6.x
  endloop
  mov r6.x, r2.y
  mov r6.y, r3.y
  mov r6.z, r5.w
  loop
    ilt r6.w, r6.x, r1.x
    ieq r7.y, r6.z, l(2)
    and r6.w, r6.w, r7.y
    breakc_z r6.w
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r7.yzw, r6.y, l(0), t2.xxyz
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r8.xyz, r6.y, l(16), t2.xyzx
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r9.xyz, r6.y, l(32), t2.xyzx
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r10.xyz, r6.y, l(48), t2.xyzx
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r11.xyz, r6.y, l(64), t2.xyzx
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r12.xyz, r6.y, l(80), t2.xyzx
    mov r6.w, l(0)
    mov r8.w, l(0)
    loop
      ige r9.w, r8.w, l(4)
      breakc_nz r9.w
      imad r9.w, r8.w, l(64), vThreadIDInGroupFlattened.x
      bfi r13.x, l(28), l(4), vThreadGroupID.x, r9.w
      ishr r9.w, r9.w, l(4)
      iadd r13.y, r1.y, r9.w
      umin r13.xy, r0.zwzz, r13.xyxx
      utof r13.xy, r13.xyxx
      add r13.xy, -r2.zwzz, r13.xyxx
      dp4 r14.z, r4.xyzw, icb[r8.w + 0].xyzw
      add r13.xy, r13.xyxx, l(0.500000, 0.500000, 0.000000, 0.000000)
      div r15.x, r13.x, cb0[r3.x + 8].x
      div r15.y, r13.y, cb0[r3.x + 9].y
      mul r13.xy, r14.zzzz, r15.xyxx
      movc r14.xy, cb0[33].wwww, r15.xyxx, r13.xyxx
      add r13.xyz, r7.yzwy, -r14.xyzx
      dp3 r14.x, r13.xyzx, r8.xyzx
      dp3 r14.y, r13.xyzx, r9.xyzx
      dp3 r14.z, r13.xyzx, r10.xyzx
      add r13.xyz, -r11.xyzx, |r14.xyzx|
      mul r13.xyz, r12.xyzx, r13.xyzx
      max r9.w, r13.y, r13.x
      max r9.w, r13.z, r9.w
      lt r9.w, r9.w, l(1.000000)
      mov r9.w, l(-1)
      movc r6.w, r9.w, l(1), r6.w
      iadd r8.w, r8.w, l(1)
    endloop
    ilt r7.y, r6.x, l(32)
    movc r7.y, r7.y, l(0), l(1)
    ishl r7.z, r6.w, r6.x
    mov r7.w, x0[r7.y + 0].x
    or r7.z, r7.z, r7.w
    mov x0[r7.y + 0].x, r7.z
    iadd r6.x, r6.x, l(1)
    ilt r7.y, r6.x, r1.x
    ld_structured r7.z, r6.x, l(0), g0.xxxx
    umin r7.z, r3.z, r7.z
    imad r7.z, vThreadID.z, cb0[33].z, r7.z
    and r6.y, r7.z, r7.y
    ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r7.z, r6.y, l(12), t2.xxxx
    and r6.z, r7.z, r7.y
  endloop
  uge r6.y, r6.z, l(3)
  iadd r2.x, -r6.y, r6.x
endloop
mov r0.z, x0[0].x
atomic_or g5, l(0, 0, 0, 0), r0.z
mov r0.z, x0[1].x
atomic_or g5, l(1, 0, 0, 0), r0.z
if_z vThreadIDInGroupFlattened.x
  store_raw g6.x, l(0), l(0)
endif
sync_g_t
ult r0.z, vThreadIDInGroupFlattened.x, r1.x
movc r0.w, r1.z, l(0), l(1)
ld_structured r0.w, r0.w, l(0), g5.xxxx
ishl r1.x, l(1), vThreadIDInGroupFlattened.x
and r0.w, r0.w, r1.x
ine r0.w, r0.w, l(0)
and r0.z, r0.w, r0.z
if_nz r0.z
  imm_atomic_iadd r2.x, g6, l(0), l(1)
  ult r0.z, r2.x, l(64)
  if_nz r0.z
    ld_structured r0.z, vThreadIDInGroupFlattened.x, l(0), g0.xxxx
    store_structured g1.x, r2.x, l(0), r0.z
  endif
endif
if_nz r1.w
  store_structured g7.x, vThreadIDInGroupFlattened.x, l(0), l(0)
endif
if_z vThreadIDInGroupFlattened.x
  store_raw g9.x, l(0), l(0)
endif
sync_g_t
ld_raw r0.z, l(0), g6.xxxx
imin r0.z, r0.z, l(64)
mov r1.y, l(0)
mov r0.w, vThreadIDInGroupFlattened.x
loop
  ige r1.z, r0.w, r0.z
  breakc_nz r1.z
  ld_structured r1.z, r0.w, l(0), g1.xxxx
  umin r1.z, r3.z, r1.z
  imad r1.z, vThreadID.z, cb0[33].z, r1.z
  ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r1.x, r1.z, l(28), t2.xxxx
  atomic_iadd g7, r1.xyxx, l(1)
  ld_structured_indexable(structured_buffer, stride=96)(mixed,mixed,mixed,mixed) r1.x, r1.z, l(76), t2.xxxx
  atomic_or g9, l(0), r1.x
  iadd r0.w, r0.w, l(64)
endloop
firstbit_hi r0.w, r0.z
iadd r0.w, -r0.w, l(31)
ishl r0.w, l(1), r0.w
movc r0.w, r0.z, r0.w, l(0)
ine r1.x, r0.z, r0.w
and r1.x, r1.x, l(1)
ishl r1.x, r0.w, r1.x
umax r0.w, r0.w, r1.x
umin r0.w, r0.w, l(64)
iadd r0.z, r0.z, vThreadIDInGroupFlattened.x
mov r1.x, r0.z
loop
  ige r1.y, r1.x, r0.w
  breakc_nz r1.y
  store_structured g1.x, r1.x, l(0), l(-1)
  iadd r1.x, r1.x, l(64)
endloop
sync_g_t
mov r0.z, l(2)
loop
  ilt r1.x, r0.w, r0.z
  breakc_nz r1.x
  ishr r1.x, r0.z, l(1)
  mov r1.y, r1.x
  loop
    ige r1.z, l(0), r1.y
    breakc_nz r1.z
    mov r1.z, vThreadIDInGroupFlattened.x
    loop
      ige r1.w, r1.z, r0.w
      breakc_nz r1.w
      xor r1.w, r1.y, r1.z
      ilt r2.x, r1.z, r1.w
      if_nz r2.x
        ld_structured r2.x, r1.z, l(0), g1.xxxx
        ld_structured r2.y, r1.w, l(0), g1.xxxx
        and r2.z, r0.z, r1.z
        movc r2.z, r2.z, l(1), l(0)
        ult r2.w, r2.y, r2.x
        and r2.w, r2.w, l(1)
        xor r2.z, r2.w, r2.z
        ine r2.z, r2.z, l(0)
        ine r2.w, r2.y, r2.x
        and r2.z, r2.w, r2.z
        if_nz r2.z
          store_structured g1.x, r1.z, l(0), r2.y
          store_structured g1.x, r1.w, l(0), r2.x
        endif
      endif
      iadd r1.z, r1.z, l(64)
    endloop
    sync_g_t
    ishr r1.y, r1.y, l(1)
  endloop
  ishl r0.z, r0.z, l(1)
endloop
if_z vThreadIDInGroupFlattened.x
  ld_raw r0.z, l(0), g9.xxxx
  or r0.z, r0.z, cb0[34].x
  ld_raw r0.w, l(0), g3.xxxx
  ld_raw r1.x, l(0), g2.xxxx
  ult r0.w, r0.w, r1.x
  movc r0.z, r0.w, l(0), r0.z
  imad r0.w, vThreadGroupID.y, r0.x, vThreadGroupID.x
  imul null, r1.x, r0.x, vThreadID.z
  imad r0.w, r1.x, r0.y, r0.w
  store_structured u1.x, r0.w, l(0), r0.z
endif
imad r0.z, vThreadGroupID.y, r0.x, vThreadGroupID.x
imul null, r0.w, r0.x, vThreadID.z
imul null, r0.w, r0.y, r0.w
imad r0.z, r0.w, l(6), r0.z
mov x1[0].x, l(0)
mov x1[1].x, l(0)
mov x1[2].x, cb0[34].z
mov x1[4].x, cb0[34].w
mov x1[3].x, cb0[35].y
mov r0.w, l(0)
mov r1.x, r0.z
mov r1.y, l(0)
loop
  ige r1.z, r1.y, l(5)
  breakc_nz r1.z
  ld_structured r1.z, r1.y, l(0), g7.xxxx
  imin r1.w, r1.z, l(24)
  iadd r2.x, r1.w, l(2)
  ishr r2.x, r2.x, l(1)
  mov r2.y, x1[r1.y + 0].x
  ishl r2.z, r1.x, l(4)
  mov r2.w, vThreadIDInGroupFlattened.x
  loop
    ige r3.x, r2.w, r2.x
    breakc_nz r3.x
    ishl r3.x, r2.w, l(1)
    iadd r3.x, r0.w, r3.x
    iadd r3.y, r3.x, l(-1)
    imax r3.y, r3.y, l(0)
    ld_structured r3.y, r3.y, l(0), g1.xxxx
    iadd r3.y, -r2.y, r3.y
    movc r3.y, r2.w, r3.y, r1.w
    ld_structured r3.x, r3.x, l(0), g1.xxxx
    iadd r3.x, -r2.y, r3.x
    iadd r3.z, r2.w, r2.z
    bfi r3.x, l(16), l(16), r3.x, r3.y
    store_structured u0.x, r3.z, l(0), r3.x
    iadd r2.w, r2.w, l(64)
  endloop
  iadd r0.w, r0.w, r1.z
  imad r1.x, r0.x, r0.y, r1.x
  iadd r1.y, r1.y, l(1)
endloop
ret
// Approximately 0 instruction slots used

///////////////////////////////// HLSL Code /////////////////////////////////
// // ---- Created with 3Dmigoto v0.6.164 on Sun Nov  8 11:19:55 2026
// groupshared struct { float val[1]; } g7[5];
// groupshared struct { float val[1]; } g5[2];
// groupshared struct { float val[1]; } g1[64];
// groupshared struct { float val[1]; } g0[64];
// struct u1_t {
//   float val[1];
// };
// RWStructuredBuffer<u1_t> u1 : register(u1);
//
// struct u0_t {
//   float val[1];
// };
// RWStructuredBuffer<u0_t> u0 : register(u0);
//
// struct t4_t {
//   float val[1];
// };
// StructuredBuffer<t4_t> t4 : register(t4);
//
// struct t3_t {
//   float val[14];
// };
// StructuredBuffer<t3_t> t3 : register(t3);
//
// struct t2_t {
//   float val[24];
// };
// StructuredBuffer<t2_t> t2 : register(t2);
//
// struct t1_t {
//   float val[4];
// };
// StructuredBuffer<t1_t> t1 : register(t1);
//
// Texture2DArray<float4> t0 : register(t0);
//
// cbuffer cb0 : register(b0)
// {
//   float4 cb0[36];
// }
//
//
//
//
// // 3Dmigoto declarations
// #define cmp -
// Texture1D<float4> IniParams : register(t120);
// Buffer<float4> StereoParams : register(t125);
//
//
// void main)
// {
//   const float4 icb[] = { { 1.000000, 0, 0, 0},
//                               { 0, 1.000000, 0, 0},
//                               { 0, 0, 1.000000, 0},
//                               { 0, 0, 0, 1.000000} };
//   float4 r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15;
//   uint4 bitmask, uiDest;
//   float4 fDest;
//
//   float4 x0[2];
//   float4 x1[5];
// // Needs manual fix for instruction:
// // unknown dcl_: dcl_tgsm_raw g2, 4
// // Needs manual fix for instruction:
// // unknown dcl_: dcl_tgsm_raw g3, 4
// // Needs manual fix for instruction:
// // unknown dcl_: dcl_tgsm_raw g4, 4
// // Needs manual fix for instruction:
// // unknown dcl_: dcl_tgsm_raw g6, 4
// // Needs manual fix for instruction:
// // unknown dcl_: dcl_tgsm_raw g8, 4
// // Needs manual fix for instruction:
// // unknown dcl_: dcl_tgsm_raw g9, 4
// // Needs manual fix for instruction:
// // unknown dcl_: dcl_thread_group 64, 1, 1
//   g1[vThreadIDInGroupFlattened.x].val[0/4] = 0;
//   r0.xyzw = asint(cb0[33].xyxy) + int4(15,15,-1,-1);
//   r0.xy = (uint2)r0.xy >> int2(4,4);
//   if (vThreadIDInGroupFlattened.x == 0) {
//   // No code for instruction (needs manual fix):
//     store_raw g2.x, l(0), l(340282346638528859811704183484516925440.000000)
//   // No code for instruction (needs manual fix):
//     store_raw g3.x, l(0), l(0)
//   // No code for instruction (needs manual fix):
//     store_raw g4.x, l(0), l(0)
//   }
//   GroupMemoryBarrierWithGroupSync();
//   r1.xy = (uint2)vThreadGroupID.xy << int2(4,4);
//   bitmask.x = ((~(-1 << 28)) << 4) & 0xffffffff;  r2.x = (((uint)vThreadGroupID.x << 4) & bitmask.x) | ((uint)vThreadIDInGroupFlattened.x & ~bitmask.x);
//   r1.z = (uint)vThreadIDInGroupFlattened.x >> 4;
//   r2.y = mad((int)vThreadGroupID.y, 16, (int)r1.z);
//   r2.xy = min((uint2)r2.xy, (uint2)r0.zw);
//   r2.z = vThreadID.z;
//   r2.w = 0;
//   r1.z = t0.Load(r2.xyzw).x;
//   r1.z = 1 + -r1.z;
//   r3.xy = (uint2)vThreadID.zz << int2(2,1);
//   r3.zw = cb0[r3.x+2].zw * r1.zz + cb0[r3.x+3].zw;
//   r4.x = r3.z / r3.w;
//   r1.w = cmp(r1.z < 1);
//   r5.x = min(3.40282347e+38, r1.z);
//   r5.y = max(0, r1.z);
//   r1.zw = r1.ww ? r5.xy : float2(3.40282347e+38,0);
//   r5.xyz = (int3)vThreadIDInGroupFlattened.xxx + int3(64,128,192);
//   bitmask.x = ((~(-1 << 28)) << 4) & 0xffffffff;  r6.x = (((uint)vThreadGroupID.x << 4) & bitmask.x) | ((uint)r5.x & ~bitmask.x);
//   bitmask.y = ((~(-1 << 28)) << 4) & 0xffffffff;  r6.y = (((uint)vThreadGroupID.x << 4) & bitmask.y) | ((uint)r5.y & ~bitmask.y);
//   bitmask.z = ((~(-1 << 28)) << 4) & 0xffffffff;  r6.z = (((uint)vThreadGroupID.x << 4) & bitmask.z) | ((uint)r5.z & ~bitmask.z);
//   r5.xyz = (uint3)r5.xyz >> int3(4,4,4);
//   r5.xyz = mad((int3)vThreadGroupID.yyy, int3(16,16,16), (int3)r5.xzy);
//   r6.w = r5.x;
//   r2.xy = min((uint2)r6.xw, (uint2)r0.zw);
//   r3.z = t0.Load(r2.xyzw).x;
//   r3.z = 1 + -r3.z;
//   r6.xw = cb0[r3.x+2].zw * r3.zz + cb0[r3.x+3].zw;
//   r4.y = r6.x / r6.w;
//   r3.w = cmp(r3.z < 1);
//   r7.x = min(r3.z, r1.z);
//   r7.y = max(r3.z, r1.w);
//   r1.zw = r3.ww ? r7.xy : r1.zw;
//   r5.xw = r6.zy;
//   r2.xy = min((uint2)r5.wz, (uint2)r0.zw);
//   r3.z = t0.Load(r2.xyzw).x;
//   r3.z = 1 + -r3.z;
//   r5.zw = cb0[r3.x+2].zw * r3.zz + cb0[r3.x+3].zw;
//   r4.z = r5.z / r5.w;
//   r3.w = cmp(r3.z < 1);
//   r6.x = min(r3.z, r1.z);
//   r6.y = max(r3.z, r1.w);
//   r1.zw = r3.ww ? r6.xy : r1.zw;
//   r2.xy = min((uint2)r5.xy, (uint2)r0.zw);
//   r2.x = t0.Load(r2.xyzw).x;
//   r2.x = 1 + -r2.x;
//   r2.yz = cb0[r3.x+2].zw * r2.xx + cb0[r3.x+3].zw;
//   r4.w = r2.y / r2.z;
//   r2.y = cmp(r2.x < 1);
//   r5.x = min(r2.x, r1.z);
//   r5.y = max(r2.x, r1.w);
//   r1.zw = r2.yy ? r5.xy : r1.zw;
//   // Needs manual fix for instruction:
// atomic_umax g3, l(0), r1.w
//   InterlockedMax(dest, value, orig_value);
//   // Needs manual fix for instruction:
// atomic_umin g2, l(0), r1.z
//   InterlockedMin(dest, value, orig_value);
//   GroupMemoryBarrierWithGroupSync();
//   r1.zw = (uint2)r1.xy;
//   r2.xy = asuint(cb0[33].xy);
//   r5.xy = r1.zw / r2.xy;
// // No code for instruction (needs manual fix):
// ld_raw r5.z, l(0), g2.xxxx
//   r1.xz = (int2)r1.xy + int2(16,16);
//   r1.xz = (uint2)r1.xz;
//   r1.xz = r1.xz / r2.xy;
// // No code for instruction (needs manual fix):
// ld_raw r2.z, l(0), g3.xxxx
//   r2.xy = min(float2(1,1), r1.xz);
//   r1.xz = (int2)r0.xy + int2(3,3);
//   r1.xz = (uint2)r1.xz >> int2(2,2);
//   r1.w = (int)r1.x * (int)vThreadID.z;
//   r3.zw = (uint2)vThreadGroupID.yx >> int2(2,2);
//   r1.x = (int)r1.x * (int)r3.z;
//   r1.x = mad((int)r1.w, (int)r1.z, (int)r1.x);
//   r1.x = (int)r3.w + (int)r1.x;
//   r1.x = (uint)r1.x << 9;
//   r1.z = t4[r1.x].val[0/4];
//   r1.w = vThreadIDInGroupFlattened.x;
//   while (true) {
//     r2.w = cmp((int)r1.w >= (int)r1.z);
//     if (r2.w != 0) break;
//     r2.w = (int)r1.w + (int)r1.x;
//     r2.w = (int)r2.w + 1;
//     r2.w = t4[r2.w].val[0/4];
//     r3.z = t2[r2.w].val[28/4];
//     r3.z = cmp((int)r3.z == 5);
//     if (r3.z != 0) {
//       break;
//     }
//     r3.z = mad((int)r3.y, asint(cb0[33].z), (int)r2.w);
//     r3.w = (int)r3.z + asint(cb0[33].z);
//     r6.x = t1[r3.z].val[0/4];
//     r6.y = t1[r3.z].val[0/4+1];
//     r6.z = t1[r3.z].val[0/4+2];
//     r7.x = t1[r3.w].val[0/4];
//     r7.y = t1[r3.w].val[0/4+1];
//     r7.z = t1[r3.w].val[0/4+2];
//     r7.xyz = cmp(r5.xyz < r7.xyz);
//     r3.z = r7.y ? r7.x : 0;
//     r3.z = r7.z ? r3.z : 0;
//     r6.xyz = cmp(r6.xyz < r2.xyz);
//     r3.w = r6.y ? r6.x : 0;
//     r3.w = r6.z ? r3.w : 0;
//     r3.z = (int)r3.w & (int)r3.z;
//     if (r3.z != 0) {
//       // Needs manual fix for instruction:
//         imm_atomic_iadd r6.x, g4, l(0), l(1)
//       InterlockedAdd(dest, imm_value, orig_value);
//       r3.z = cmp((uint)r6.x < 64);
//       if (r3.z != 0) {
//         g0[r6.x].val[0/4] = r2.w;
//       }
//     }
//     r1.w = (int)r1.w + 64;
//   }
//   r1.xzw = cmp((uint3)vThreadIDInGroupFlattened.xxx < int3(2,32,5));
//   if (r1.x != 0) {
//     g5[vThreadIDInGroupFlattened.x].val[0/4] = 0;
//   }
//   GroupMemoryBarrierWithGroupSync();
// // No code for instruction (needs manual fix):
// ld_raw r1.x, l(0), g4.xxxx
//   r1.x = min(64, (uint)r1.x);
//   r2.xy = mad((int2)vThreadGroupID.xy, int2(16,16), int2(8,8));
//   r2.xy = min((uint2)r2.xy, (uint2)r0.zw);
//   r2.xy = (uint2)r2.xy;
//   if (vThreadIDInGroupFlattened.x == 0) {
//   // No code for instruction (needs manual fix):
//     store_raw g8.x, l(0), l(0)
//   }
//   r2.z = vThreadIDInGroupFlattened.x;
//   while (true) {
//     r2.w = cmp((int)r2.z >= (int)r1.x);
//     if (r2.w != 0) break;
//     r2.w = g0[r2.z].val[0/4];
//     g1[r2.z].val[0/4] = r2.w;
//     r2.z = (int)r2.z + 64;
//   }
//   GroupMemoryBarrierWithGroupSync();
//   r2.zw = cb0[33].ww ? cb0[r3.x+11].xy : cb0[r3.x+10].xy;
//   r2.xy = r2.xy + -r2.zw;
//   r2.x = r2.x / cb0[r3.x+8].x;
//   r2.y = r2.y / cb0[r3.x+9].y;
//   r5.x = 1 / cb0[r3.x+8].x;
//   r5.y = 1 / cb0[r3.x+9].y;
//   r3.y = dot(r5.xy, r5.xy);
//   r3.y = sqrt(r3.y);
//   r3.y = 8 * r3.y;
//   r3.z = asint(cb0[33].z) + -1;
//   r5.xy = cb0[33].ww ? float2(0,0) : r2.xy;
//   r2.xy = cb0[33].ww ? -r2.xy : float2(-0,-0);
//   r5.z = 1;
//   r3.w = dot(r5.xyz, r5.xyz);
//   r5.w = vThreadIDInGroupFlattened.x;
//   while (true) {
//     r6.x = cmp((int)r5.w >= (int)r1.x);
//     if (r6.x != 0) break;
//     r6.x = g1[r5.w].val[0/4];
//     r6.y = min((uint)r6.x, (uint)r3.z);
//     r6.y = mad((int)vThreadID.z, asint(cb0[33].z), (int)r6.y);
//     r7.x = t3[r6.y].val[36/4];
//     r7.y = t3[r6.y].val[36/4+1];
//     r7.z = t3[r6.y].val[36/4+2];
//     r6.y = t3[r6.y].val[52/4];
//     r7.xy = r7.xy + r2.xy;
//     r8.xy = -r7.zz * r7.xy;
//     r8.z = dot(r7.xy, r7.xy);
//     r6.z = dot(r8.xyz, r8.xyz);
//     r6.z = sqrt(r6.z);
//     r6.w = cmp(9.99999975e-05 < r6.z);
//     r7.w = r8.z / r6.z;
//     r6.z = r6.w ? r7.w : r6.z;
//     r6.z = r6.z * r6.y + r7.z;
//     r6.z = cb0[33].w ? 1 : r6.z;
//     r6.y = r6.z * r3.y + r6.y;
//     r6.z = dot(r7.xyz, r5.xyz);
//     r6.w = dot(r7.xyz, r7.xyz);
//     r6.y = -r6.y * r6.y + r6.w;
//     r6.w = r6.y * r3.w;
//     r6.w = r6.z * r6.z + -r6.w;
//     r6.y = cmp(r6.y < 0);
//     r6.zw = cmp(float2(0,0) < r6.zw);
//     r6.z = r6.z ? r6.w : 0;
//     r6.y = (int)r6.z | (int)r6.y;
//     if (r6.y != 0) {
//       // Needs manual fix for instruction:
//         imm_atomic_iadd r7.x, g8, l(0), l(1)
//       InterlockedAdd(dest, imm_value, orig_value);
//       g0[r7.x].val[0/4] = r6.x;
//     }
//     r5.w = (int)r5.w + 64;
//   }
//   GroupMemoryBarrierWithGroupSync();
// // No code for instruction (needs manual fix):
// ld_raw r1.x, l(0), g8.xxxx
//   x0[0].x = 0;
//   x0[1].x = 0;
//   r2.x = 0;
//   while (true) {
//     r2.y = cmp((int)r2.x >= (int)r1.x);
//     if (r2.y != 0) break;
//     r2.y = cmp((int)r2.x < (int)r1.x);
//     r3.y = g0[r2.x].val[0/4];
//     r3.y = min((uint)r3.y, (uint)r3.z);
//     r3.y = mad((int)vThreadID.z, asint(cb0[33].z), (int)r3.y);
//     r3.y = r2.y ? r3.y : 0;
//     r3.w = t2[r3.y].val[12/4];
//     r2.y = r2.y ? r3.w : 0;
//     r3.w = r2.x;
//     r5.x = r3.y;
//     r5.y = r2.y;
//     while (true) {
//       r5.z = cmp((int)r3.w < (int)r1.x);
//       r5.w = cmp((int)r5.y == 0);
//       r5.z = r5.w ? r5.z : 0;
//       if (r5.z == 0) break;
//       r6.x = t2[r5.x].val[0/4];
//       r6.y = t2[r5.x].val[0/4+1];
//       r6.z = t2[r5.x].val[0/4+2];
//       r7.x = t2[r5.x].val[16/4];
//       r7.y = t2[r5.x].val[16/4+1];
//       r7.z = t2[r5.x].val[16/4+2];
//       r8.x = t2[r5.x].val[32/4];
//       r8.y = t2[r5.x].val[32/4+1];
//       r8.z = t2[r5.x].val[32/4+2];
//       r8.w = t2[r5.x].val[32/4+3];
//       r9.x = t2[r5.x].val[48/4];
//       r9.y = t2[r5.x].val[48/4+1];
//       r9.z = t2[r5.x].val[48/4+2];
//       r9.w = t2[r5.x].val[48/4+3];
//       r10.x = r8.w;
//       r5.zw = float2(0,0);
//       while (true) {
//         r6.w = cmp((int)r5.w >= 4);
//         if (r6.w != 0) break;
//         r6.w = mad((int)r5.w, 64, (int)vThreadIDInGroupFlattened.x);
//         bitmask.x = ((~(-1 << 28)) << 4) & 0xffffffff;  r11.x = (((uint)vThreadGroupID.x << 4) & bitmask.x) | ((uint)r6.w & ~bitmask.x);
//         r6.w = (uint)r6.w >> 4;
//         r11.y = (int)r1.y + (int)r6.w;
//         r10.zw = min((uint2)r11.xy, (uint2)r0.zw);
//         r10.zw = (uint2)r10.zw;
//         r10.zw = r10.zw + -r2.zw;
//         r11.z = dot(r4.xyzw, icb[r5.w+0].xyzw);
//         r10.zw = float2(0.5,0.5) + r10.zw;
//         r12.x = r10.z / cb0[r3.x+8].x;
//         r12.y = r10.w / cb0[r3.x+9].y;
//         r10.zw = r12.xy * r11.zz;
//         r11.xy = cb0[33].ww ? r12.xy : r10.zw;
//         r11.xyz = r11.xyz + -r6.xyz;
//         r12.x = dot(r11.xyz, r11.xyz);
//         r10.y = dot(r11.xyz, r9.xyz);
//         r13.x = dot(r11.xyz, r7.xyz);
//         r13.y = dot(r11.xyz, r8.xyz);
//         r6.w = dot(abs(r13.xy), abs(r13.xy));
//         r6.w = sqrt(r6.w);
//         r12.y = r6.w * r9.w;
//         r10.yz = cmp(r12.xy < r10.xy);
//         r6.w = r10.z ? r10.y : 0;
//         r5.z = r6.w ? 1 : r5.z;
//         r5.w = (int)r5.w + 1;
//       }
//       r5.w = cmp((int)r3.w < 32);
//       r5.w = r5.w ? 0 : 1;
//       r6.x = (uint)r5.z << (int)r3.w;
//       r6.y = x0[r5.w+0].x;
//       r6.x = (int)r6.x | (int)r6.y;
//       x0[r5.w+0].x = r6.x;
//       r3.w = (int)r3.w + 1;
//       r5.w = cmp((int)r3.w < (int)r1.x);
//       r6.x = g0[r3.w].val[0/4];
//       r6.x = min((uint)r6.x, (uint)r3.z);
//       r6.x = mad((int)vThreadID.z, asint(cb0[33].z), (int)r6.x);
//       r5.x = r5.w ? r6.x : 0;
//       r6.x = t2[r5.x].val[12/4];
//       r5.y = r5.w ? r6.x : 0;
//     }
//     r2.y = r3.w;
//     r3.y = r5.x;
//     r5.w = r5.y;
//     while (true) {
//       r6.x = cmp((int)r2.y < (int)r1.x);
//       r6.y = cmp((int)r5.w == 1);
//       r6.x = r6.y ? r6.x : 0;
//       if (r6.x == 0) break;
//       r6.x = t2[r3.y].val[0/4];
//       r6.y = t2[r3.y].val[0/4+1];
//       r6.z = t2[r3.y].val[0/4+2];
//       r6.w = t2[r3.y].val[44/4];
//       r7.xy = float2(0,0);
//       while (true) {
//         r7.z = cmp((int)r7.y >= 4);
//         if (r7.z != 0) break;
//         r7.z = mad((int)r7.y, 64, (int)vThreadIDInGroupFlattened.x);
//         bitmask.x = ((~(-1 << 28)) << 4) & 0xffffffff;  r8.x = (((uint)vThreadGroupID.x << 4) & bitmask.x) | ((uint)r7.z & ~bitmask.x);
//         r7.z = (uint)r7.z >> 4;
//         r8.y = (int)r1.y + (int)r7.z;
//         r7.zw = min((uint2)r8.xy, (uint2)r0.zw);
//         r7.zw = (uint2)r7.zw;
//         r7.zw = r7.zw + -r2.zw;
//         r8.z = dot(r4.xyzw, icb[r7.y+0].xyzw);
//         r7.zw = float2(0.5,0.5) + r7.zw;
//         r9.x = r7.z / cb0[r3.x+8].x;
//         r9.y = r7.w / cb0[r3.x+9].y;
//         r7.zw = r9.xy * r8.zz;
//         r8.xy = cb0[33].ww ? r9.xy : r7.zw;
//         r8.xyz = -r8.xyz + r6.xyz;
//         r7.z = dot(r8.xyz, r8.xyz);
//         r7.z = cmp(r7.z < r6.w);
//         r7.x = r7.z ? 1 : r7.x;
//         r7.y = (int)r7.y + 1;
//       }
//       r6.x = cmp((int)r2.y < 32);
//       r6.x = r6.x ? 0 : 1;
//       r6.y = (uint)r7.x << (int)r2.y;
//       r6.z = x0[r6.x+0].x;
//       r6.y = (int)r6.y | (int)r6.z;
//       x0[r6.x+0].x = r6.y;
//       r2.y = (int)r2.y + 1;
//       r6.x = cmp((int)r2.y < (int)r1.x);
//       r6.y = g0[r2.y].val[0/4];
//       r6.y = min((uint)r6.y, (uint)r3.z);
//       r6.y = mad((int)vThreadID.z, asint(cb0[33].z), (int)r6.y);
//       r3.y = r6.x ? r6.y : 0;
//       r6.y = t2[r3.y].val[12/4];
//       r5.w = r6.x ? r6.y : 0;
//     }
//     r6.x = r2.y;
//     r6.y = r3.y;
//     r6.z = r5.w;
//     while (true) {
//       r6.w = cmp((int)r6.x < (int)r1.x);
//       r7.y = cmp((int)r6.z == 2);
//       r6.w = r6.w ? r7.y : 0;
//       if (r6.w == 0) break;
//       r7.y = t2[r6.y].val[0/4];
//       r7.z = t2[r6.y].val[0/4+1];
//       r7.w = t2[r6.y].val[0/4+2];
//       r8.x = t2[r6.y].val[16/4];
//       r8.y = t2[r6.y].val[16/4+1];
//       r8.z = t2[r6.y].val[16/4+2];
//       r9.x = t2[r6.y].val[32/4];
//       r9.y = t2[r6.y].val[32/4+1];
//       r9.z = t2[r6.y].val[32/4+2];
//       r10.x = t2[r6.y].val[48/4];
//       r10.y = t2[r6.y].val[48/4+1];
//       r10.z = t2[r6.y].val[48/4+2];
//       r11.x = t2[r6.y].val[64/4];
//       r11.y = t2[r6.y].val[64/4+1];
//       r11.z = t2[r6.y].val[64/4+2];
//       r12.x = t2[r6.y].val[80/4];
//       r12.y = t2[r6.y].val[80/4+1];
//       r12.z = t2[r6.y].val[80/4+2];
//       r6.w = 0;
//       r8.w = 0;
//       while (true) {
//         r9.w = cmp((int)r8.w >= 4);
//         if (r9.w != 0) break;
//         r9.w = mad((int)r8.w, 64, (int)vThreadIDInGroupFlattened.x);
//         bitmask.x = ((~(-1 << 28)) << 4) & 0xffffffff;  r13.x = (((uint)vThreadGroupID.x << 4) & bitmask.x) | ((uint)r9.w & ~bitmask.x);
//         r9.w = (uint)r9.w >> 4;
//         r13.y = (int)r1.y + (int)r9.w;
//         r13.xy = min((uint2)r13.xy, (uint2)r0.zw);
//         r13.xy = (uint2)r13.xy;
//         r13.xy = r13.xy + -r2.zw;
//         r14.z = dot(r4.xyzw, icb[r8.w+0].xyzw);
//         r13.xy = float2(0.5,0.5) + r13.xy;
//         r15.x = r13.x / cb0[r3.x+8].x;
//         r15.y = r13.y / cb0[r3.x+9].y;
//         r13.xy = r15.xy * r14.zz;
//         r14.xy = cb0[33].ww ? r15.xy : r13.xy;
//         r13.xyz = -r14.xyz + r7.yzw;
//         r14.x = dot(r13.xyz, r8.xyz);
//         r14.y = dot(r13.xyz, r9.xyz);
//         r14.z = dot(r13.xyz, r10.xyz);
//         r13.xyz = abs(r14.xyz) + -r11.xyz;
//         r13.xyz = r13.xyz * r12.xyz;
//         r9.w = max(r13.x, r13.y);
//         r9.w = max(r9.w, r13.z);
//         r9.w = cmp(r9.w < 1);
//         r6.w = r9.w ? 1 : r6.w;
//         r8.w = (int)r8.w + 1;
//       }
//       r7.y = cmp((int)r6.x < 32);
//       r7.y = r7.y ? 0 : 1;
//       r7.z = (uint)r6.w << (int)r6.x;
//       r7.w = x0[r7.y+0].x;
//       r7.z = (int)r7.z | (int)r7.w;
//       x0[r7.y+0].x = r7.z;
//       r6.x = (int)r6.x + 1;
//       r7.y = cmp((int)r6.x < (int)r1.x);
//       r7.z = g0[r6.x].val[0/4];
//       r7.z = min((uint)r7.z, (uint)r3.z);
//       r7.z = mad((int)vThreadID.z, asint(cb0[33].z), (int)r7.z);
//       r6.y = r7.y ? r7.z : 0;
//       r7.z = t2[r6.y].val[12/4];
//       r6.z = r7.y ? r7.z : 0;
//     }
//     r6.y = cmp((uint)r6.z >= 3);
//     r2.x = (int)-r6.y + (int)r6.x;
//   }
//   r0.z = x0[0].x;
//   // Needs manual fix for instruction:
// atomic_or g5, l(0, 0, 0, 0), r0.z
//   InterlockedOr(dest, value, orig_value);
//   r0.z = x0[1].x;
//   // Needs manual fix for instruction:
// atomic_or g5, l(1, 0, 0, 0), r0.z
//   InterlockedOr(dest, value, orig_value);
//   if (vThreadIDInGroupFlattened.x == 0) {
//   // No code for instruction (needs manual fix):
//     store_raw g6.x, l(0), l(0)
//   }
//   GroupMemoryBarrierWithGroupSync();
//   r0.z = cmp((uint)vThreadIDInGroupFlattened.x < (uint)r1.x);
//   r0.w = r1.z ? 0 : 1;
//   r0.w = g5[r0.w].val[0/4];
//   r1.x = 1 << (int)vThreadIDInGroupFlattened.x;
//   r0.w = (int)r0.w & (int)r1.x;
//   r0.w = cmp((int)r0.w != 0);
//   r0.z = r0.w ? r0.z : 0;
//   if (r0.z != 0) {
//     // Needs manual fix for instruction:
//     imm_atomic_iadd r2.x, g6, l(0), l(1)
//     InterlockedAdd(dest, imm_value, orig_value);
//     r0.z = cmp((uint)r2.x < 64);
//     if (r0.z != 0) {
//       r0.z = g0[vThreadIDInGroupFlattened.x].val[0/4];
//       g1[r2.x].val[0/4] = r0.z;
//     }
//   }
//   if (r1.w != 0) {
//     g7[vThreadIDInGroupFlattened.x].val[0/4] = 0;
//   }
//   if (vThreadIDInGroupFlattened.x == 0) {
//   // No code for instruction (needs manual fix):
//     store_raw g9.x, l(0), l(0)
//   }
//   GroupMemoryBarrierWithGroupSync();
// // No code for instruction (needs manual fix):
// ld_raw r0.z, l(0), g6.xxxx
//   r0.z = min(64, (int)r0.z);
//   r1.y = 0;
//   r0.w = vThreadIDInGroupFlattened.x;
//   while (true) {
//     r1.z = cmp((int)r0.w >= (int)r0.z);
//     if (r1.z != 0) break;
//     r1.z = g1[r0.w].val[0/4];
//     r1.z = min((uint)r1.z, (uint)r3.z);
//     r1.z = mad((int)vThreadID.z, asint(cb0[33].z), (int)r1.z);
//     r1.x = t2[r1.z].val[28/4];
//     // Needs manual fix for instruction:
//     atomic_iadd g7, r1.xyxx, l(1)
//     InterlockedAdd(dest, value, orig_value);
//     r1.x = t2[r1.z].val[76/4];
//     // Needs manual fix for instruction:
//     atomic_or g9, l(0), r1.x
//     InterlockedOr(dest, value, orig_value);
//     r0.w = (int)r0.w + 64;
//   }
//   r0.w = firstbithigh((uint)r0.z);
//   r0.w = (int)-r0.w + 31;
//   r0.w = 1 << (int)r0.w;
//   r0.w = r0.z ? r0.w : 0;
//   r1.x = cmp((int)r0.z != (int)r0.w);
//   r1.x = r1.x ? 0.000000 : 0;
//   r1.x = (uint)r0.w << (int)r1.x;
//   r0.w = max((uint)r1.x, (uint)r0.w);
//   r0.w = min(64, (uint)r0.w);
//   r0.z = (int)r0.z + (int)vThreadIDInGroupFlattened.x;
//   r1.x = r0.z;
//   while (true) {
//     r1.y = cmp((int)r1.x >= (int)r0.w);
//     if (r1.y != 0) break;
//     g1[r1.x].val[0/4] = -1;
//     r1.x = (int)r1.x + 64;
//   }
//   GroupMemoryBarrierWithGroupSync();
//   r0.z = 2;
//   while (true) {
//     r1.x = cmp((int)r0.w < (int)r0.z);
//     if (r1.x != 0) break;
//     r1.x = (uint)r0.z >> 1;
//     r1.y = r1.x;
//     while (true) {
//       r1.z = cmp(0 >= (int)r1.y);
//       if (r1.z != 0) break;
//       r1.z = vThreadIDInGroupFlattened.x;
//       while (true) {
//         r1.w = cmp((int)r1.z >= (int)r0.w);
//         if (r1.w != 0) break;
//         r1.w = (int)r1.y ^ (int)r1.z;
//         r2.x = cmp((int)r1.z < (int)r1.w);
//         if (r2.x != 0) {
//           r2.x = g1[r1.z].val[0/4];
//           r2.y = g1[r1.w].val[0/4];
//           r2.z = (int)r0.z & (int)r1.z;
//           r2.z = r2.z ? 1 : 0;
//           r2.w = cmp((uint)r2.y < (uint)r2.x);
//           r2.w = r2.w ? 0.000000 : 0;
//           r2.z = (int)r2.w ^ (int)r2.z;
//           r2.z = cmp((int)r2.z != 0);
//           r2.w = cmp((int)r2.y != (int)r2.x);
//           r2.z = r2.w ? r2.z : 0;
//           if (r2.z != 0) {
//             g1[r1.z].val[0/4] = r2.y;
//             g1[r1.w].val[0/4] = r2.x;
//           }
//         }
//         r1.z = (int)r1.z + 64;
//       }
//       GroupMemoryBarrierWithGroupSync();
//       r1.y = (uint)r1.y >> 1;
//     }
//     r0.z = (uint)r0.z << 1;
//   }
//   if (vThreadIDInGroupFlattened.x == 0) {
//   // No code for instruction (needs manual fix):
//     ld_raw r0.z, l(0), g9.xxxx
//     r0.z = (int)r0.z | asint(cb0[34].x);
//   // No code for instruction (needs manual fix):
//     ld_raw r0.w, l(0), g3.xxxx
//   // No code for instruction (needs manual fix):
//     ld_raw r1.x, l(0), g2.xxxx
//     r0.w = cmp((uint)r0.w < (uint)r1.x);
//     r0.z = r0.w ? 0 : r0.z;
//     r0.w = mad((int)vThreadGroupID.y, (int)r0.x, (int)vThreadGroupID.x);
//     r1.x = (int)r0.x * (int)vThreadID.z;
//     r0.w = mad((int)r1.x, (int)r0.y, (int)r0.w);
//     u1[r0.w].val[0/4] = r0.z;
//   }
//   r0.z = mad((int)vThreadGroupID.y, (int)r0.x, (int)vThreadGroupID.x);
//   r0.w = (int)r0.x * (int)vThreadID.z;
//   r0.w = (int)r0.y * (int)r0.w;
//   r0.z = mad((int)r0.w, 6, (int)r0.z);
//   x1[0].x = 0;
//   x1[1].x = 0;
//   x1[2].x = cb0[34].z;
//   x1[4].x = cb0[34].w;
//   x1[3].x = cb0[35].y;
//   r0.w = 0;
//   r1.x = r0.z;
//   r1.y = 0;
//   while (true) {
//     r1.z = cmp((int)r1.y >= 5);
//     if (r1.z != 0) break;
//     r1.z = g7[r1.y].val[0/4];
//     r1.w = min(24, (int)r1.z);
//     r2.x = (int)r1.w + 2;
//     r2.x = (uint)r2.x >> 1;
//     r2.y = x1[r1.y+0].x;
//     r2.z = (uint)r1.x << 4;
//     r2.w = vThreadIDInGroupFlattened.x;
//     while (true) {
//       r3.x = cmp((int)r2.w >= (int)r2.x);
//       if (r3.x != 0) break;
//       r3.x = (uint)r2.w << 1;
//       r3.x = (int)r0.w + (int)r3.x;
//       r3.y = (int)r3.x + -1;
//       r3.y = max(0, (int)r3.y);
//       r3.y = g1[r3.y].val[0/4];
//       r3.y = (int)-r2.y + (int)r3.y;
//       r3.y = r2.w ? r3.y : r1.w;
//       r3.x = g1[r3.x].val[0/4];
//       r3.x = (int)-r2.y + (int)r3.x;
//       r3.z = (int)r2.w + (int)r2.z;
//       bitmask.x = ((~(-1 << 16)) << 16) & 0xffffffff;  r3.x = (((uint)r3.x << 16) & bitmask.x) | ((uint)r3.y & ~bitmask.x);
//       u0[r3.z].val[0/4] = r3.x;
//       r2.w = (int)r2.w + 64;
//     }
//     r0.w = (int)r0.w + (int)r1.z;
//     r1.x = mad((int)r0.x, (int)r0.y, (int)r1.x);
//     r1.y = (int)r1.y + 1;
//   }
//   return;
// }
//////////////////////////////// HLSL Errors ////////////////////////////////
// C:\Program Files (x86)\Steam\steamapps\common\FAR Changing Tides\ShaderFixes\84b87afcd6fd4658-cs_replace.txt(52,10): error X3000: syntax error: unexpected token ')'
/////////////////////////////////////////////////////////////////////////////
